EE 3541  -  Introduction to Microprocessors (EE3541)
Units Hours
Theoretical Practical
1 0 0
Course Catalog Description
Course Requirements
Grading Policy
Evaluation Type Weight
   1 .  First Mid. Term Exam 20 % ()
   2 .  Second Mid. Term Exam 20 % ()
   3 .  Final Term Exam 40 % ()
   4 .  Quizzes 10 % ()
   5 .  Assignments and mini projects 10 % ()
Learning Outcome
Outcome Proficiency Assessment
   1 .  (a) an ability to apply knowledge of mathematics, science, and engineering: Student has the ability to understand architecture and software model, instruction set, assembly language programming, memory and input/output interface for 8088/8086.
   2 .  (c) an ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability: Student has the ability to desi
   3 .  (e) an ability to identify, formulate, and solve engineering problems: Student has the ability to Identify, formulate, and solve engineering problems in the design of I/O interface and memory interface.
   4 .  (g) an ability to communicate effectively: Student has the ability to present a mini-project in the future trends of microprocessors.
   5 .  (k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice: Student is encouraged to use the techniques, skills, and modern engineering tools such as Assembly Language to use I/O devices and memory in solving
Week Description - Reading  

General Introduction to the course, the philosophy of teaching, assessment and overall content. Introduction to microprocessors. Overview of computer structure and operation, microprocessor evolution and types, the INTEL family of microprocessors.



Introduction/Chapter Objectives

1.1 Introduction to microprocessors

1.2 General architecture of microcomputer system

1.3 Evolution of Intel microprocessors

1.4 Architectural compatibility

1.5 Hardware and software

1.6 Review of the basic number systems and conversion between different number systems


8086/8088 Microprocessors. Basic 8086/8088 architecture, programming model, data format, instruction set. Segment registers and memory segmentation. Pointer and index register, Status and flag register, and the stack.


CHAPTER (2) Basic Architecture of the 8088 and 8086 microprocessors

Introduction/Chapter Objectives

2.1 Internal architecture of the 8086/8088 microprocessors

2.2 Memory address space and data organization

2.3 Data types

2.4 Segment registers and memory segmentation

2.5 Pointer and index register

2.6 Status and flag register

2.7 The Stack

Assessment Method:

Homework-1: Due Date: Tuesday/Week No. (2)

Quiz-1: Date: Tuesday/Week No. (2)


Addressing Modes. Data-addressing modes, register addressing, immediate addressing, direct data addressing, base-plus index addressing, register relative addressing, base relative plus index addressing program memory addressing modes. Introduction to Stack Memory-Addressing Modes.



Introduction/Chapter Objectives

3.1 Data-Addressing Modes

3.1.1 Register Addressing

3.1.2 Immediate Addressing

3.1.3 Direct Data Addressing

3.1.4 Register Indirect Addressing

3.1.5 Base-Plus-Index Addressing

3.1.6 Register Relative Addressing

3.1.7 Base Relative-Plus-Index Addressing

3.1.8 Scaled-Index Addressing

3.1.9 RIP Relative Addressing

3.1.10 Data Structures

3.2 Program Memory-Addressing Modes

3.2.1 Direct Program Memory Addressing

3.2.2 Relative Program Memory Addressing

3.2.3 Indirect Program Memory Addressing

3.3 Stack Memory-Addressing Modes

Assessment Method:

Homework-2: Due Date: Tuesday/Week No. (3)

Quiz-2: Date: Tuesday/Week No. (3)


Data Movement Instructions. MOV instruction, PUSH/POP instruction, load effective address, string data transfer, data transfer instruction. Miscellaneous Data Transfer Instructions.



Introduction/Chapter Objectives

4.1 MOV Revisited


4.2.1 PUSH

4.2.2 POP

4.2.3 Initializing the Stack

4.3 Load-Effective Address

4.3.1 LEA

4.3.2 LDS

4.3.3 LES

4.4 String Data Transfers

4.4.1 The Direction Flag

4.4.2 DI and SI

4.4.3 LODS

4.4.5 STOS

4.4.6 MOVS

4.5 Miscellaneous Data Transfer Instructions

4.5.1 XCHG

4.5.2 LAHF and SAHF


4.5.4 MOVSX and MOVZX

4.5.5 BSWAP

Assessment Method:

Homework-3: Due Date: Tuesday/Week No. (4)

Quiz-3: Date: Tuesday/Week No. (4)


Arithmetic and Logic Instruction. Addition, subtraction and comparison instruction and division, BCD and ASCII arithmetic, basic logic operation, shift and rotates, string comparison.



Introduction/Chapter Objectives

5.1 Arithmetic Instructions

5.1.1 Addition, Subtraction, and Comparison

5.1.2 Multiplication and Division

5.1.3 BCD and ASCII Arithmetic

5.2 Basic Logic Instructions

5.2.1 AND

5.2.2 OR

5.2.3 Test and Bit Test Instructions

5.2.4 NOT and NEG

5.3 Shift and Rotate

5.3.1 Shift

5.3.2 Rotate

5.3.3 Bit Scan Instructions

5.4 String Comparisons

5.4.1 SCAS

5.4.2 CMPS

Assessment Method:

Homework-4: Due Date: Tuesday/Week No. (5)

Quiz-4: Date: Tuesday/Week No. (5)


Program Control Instruction. Jump instructions, Controlling the Flow of the Program, subroutines, interrupts, Machine Control and Miscellaneous Instructions.



Introduction/Chapter Objectives

6.1 The Jump Group

6.1.1 Unconditional Jump (JMP)

6.1.2 Conditional Jumps and Conditional Sets

6.2 Controlling the Flow of the Program

6.2.1 LOOP

6.2.2 REPEAT

6.3 Procedures

6.3.1 CALL

6.3.2 RET

6.4 Introduction to Interrupts

6.4.1 Interrupt Vectors

6.4.2 Interrupt Instructions

6.4.3 Interrupt Control

6.5 Machine Control and Miscellaneous Instructions

6.5.1 Flag Control Instructions

6.5.2 WAIT

6.5.3 HLT

6.6.4 NOP

Assessment Method:

Homework-5: Due Date: Tuesday/Week No. (6)

Quiz-5: Date: Tuesday/Week No. (6)


Introduction to assembly language programming.

8 and 9

8086/8088 Hardware Specifications. Pin outs and pin functions, the 8284 clock generator, bus buffering and latching, bus timings, ready and wait states, minimum and maximum modes.



Introduction/Chapter Objectives

7.1 Pin-Outs and the Pin Functions

7.1.1 The Pin-Out

7.1.2 Power Supply Requirements

7.1.3 DC Characteristics

7.1.4 Pin Connections

7.2 Clock Generator (8284A)

7.2.1 The 8284A Clock Generator

7.2.2 Operation of the 8284A

7.3 Bus Buffering and Latching

7.3.1 Demultiplexing the Buses

7.3.2 The Buffered System

7.4 Bus Timing

7.4.1 Basic Bus Operation

7.4.2 Timing in General

7.4.3 Read Timing

7.4.4 Write Timing

7.5 Ready and the Wait State

7.5.1 The READY Input

7.5.2 RDY and the 8284A

7.6 Minimum Mode versus Maximum Mode

7.6.1 Minimum Mode Operation

7.6.2 Maximum Mode Operation

7.6.3 The 8288 Bus Controller

7.6.4 Pin Functions

Assessment Method:

First Mid Term Exam: Date: Thursday/Week No. (8)

Homework-6: Due Date: Tuesday/Week No. (9)

Quiz-6: Date: Tuesday/Week No. (9)


Memory interface. Memory devices, address decoding,



Introduction/Chapter Objectives

8.1 Memory Devices

8.1.1 Memory Pin Connections

8.1.2 ROM Memory

8.1.3 Static RAM (SRAM) Devices

8.1.4 Dynamic RAM (DRAM) Memory

8.2 Address Decoding

8.2.1 Why Decode Memory?

8.2.2 Simple NAND Gate Decoder

8.2.3 The 3-to-8 Line Decoder (74LS138)

8.2.4 The Dual 2-to-4 Line Decoder (74LS139)

8.2.5 PLD Programmable Decoders

Assessment Method:

Homework-7: Due Date: Tuesday/Week No. (10)

Quiz-7: Date: Tuesday/Week No. (10)

11 and 12

Basic I/O Interface. I/O port address decoding, the 8255 programmable peripheral device,



Introduction/Chapter Objectives

9.1 Introduction to I/O Interface

9.1.1 The I/O Instructions

9.1.2 Isolated and Memory-Mapped I/O

9.1.3 Basic Input and Output Interfaces

9.1.4 Notes about Interfacing Circuitry

9.2 I/O Port Address Decoding

9.2.1 Decoding 8-Bit I/O Port Addresses

9.2.2 Decoding 16-Bit I/O Port Addresses

9.3 The Programmable Peripheral Interface

9.3.1 Basic Description of the 82C55

9.3.2 Programming the 82C55

9.3.3 Mode 0 Operation

9.3.4 Mode 1 Strobed Input

9.3.5 Signal Definitions for Mode 1 Strobed Input

9.3.6 Mode 1 Strobed Output

9.3.7 Signal Definitions for Mode 1 Strobed Output

9.3.8 Mode 2 Bidirectional Operation

9.3.9 Signal Definitions for Bidirectional Mode 2

9.3.10 82C55 Mode Summary

9.4 8254 Programmable Interval Timer

9.4.1 8254 Functional Description

9.4.2 Pin Definitions

9.4.3 Programming the 8254

9.4.4 DC Motor Speed and Direction Control

9.5 Analog-to-Digital (ADC) and Digital-to-Analog (DAC) Converters

9.5.1 The DAC0830 Digital-to-Analog Converter

9.5.2 The ADC080X Analog-to-Digital Converter

9.5.3 Using the ADC0804 and the DAC0830

Assessment Method:

Second Mid Term Exam: Date: Thursday/Week No. (12)

Homework-8: Due Date: Tuesday/Week No. (11)

Quiz-8: Date: Tuesday/Week No. (11)

13 and 14

Interrupts. Basic interrupt processing, hardware interrupts, 8259 programmable interrupt controller.



  Introduction/Chapter Objectives

10.1 Basic Interrupt Processing

10.1.1 The Purpose of Interrupts

10.1.2 Interrupts

10.1.3 Interrupt Instructions: INTO, INT, INT 3, and IRET

10.1.4 The Operation of a Real Mode Interrupt

10.1.5 Operation of a Protected Mode Interrupt

10.1.6 Interrupt Flag Bits

10.1.7 Storing an Interrupt Vector in the Vector Table

10.2 Hardware Interrupts

10.2.1 INTR and

10.3 8259A Programmable Interrupt Controller

10.3.1 General Description of the 8259A

10.3.2 Connecting a Single 8259A

10.3.3 Programming the 8259A

10.3.4 8259A Programming Example

Assessment Method:

Homework-9: Due Date: Tuesday/Week No. (14)

Quiz-9: Date: Tuesday/Week No. (14)


Research in Future trends in microprocessors. The 80186, 80188, and 80286 Microprocessors. The 80386 and 80486 microprocessors. The Pentium and Pentium Pro Microprocessors. The Pentium II, Pentium III, and Pentium 4. 


Chapter (11) Future Trends in Microprocessors

  Introduction/Chapter Objectives

11.1 The 80186, 80188, and 80286 Microprocessors

11.2 The 80386 and 80486 microprocessors

11.3 The Pentium and Pentium Pro Microprocessors

11.4 The Pentium II, Pentium III, and Pentium 4

Assessment Method:

Students are required to make presentations for their projects one week before the end of semester with the submission of report.

Presentations: Due Date: Thursday /Week No. (15)


Assessment Method:

Final Term Exam: As Organized by Exams Committee